ISO/IEC JTC1 SC22 WG14 N1417 - 2009-10-27
Paul E. McKenney, paulmck@linux.vnet.ibm.com
WG21 added memory fences to their working draft to ease migration of current practice to the C++0x standard, choosing semantics that can be readily implemented on current multicore/parallel systems. Memory fences are often provided in concurrent C and C++ programming environments, usually in the form of platform-dependent inline assembly. Adding memory fences to the standard promotes portability.
The purpose of this document is informative. If there is interest, a document proposing changes will follow.
The remainder of this document summarizes the definition of fences in the C++ working draft N2960.
memory_order_seq_cst
fence X sequenced before B, then B observes either the last
memory_order_seq_cst
modification of M preceding
X in the total order S or a later modification of M in its
modification order.
memory_order_seq_cst
fence X such that A is sequenced
before X and B follows X in S, then B observes either the effects
of A or a later modification of M in its modification order.
memory_order_seq_cst
fences X and Y such that A is
sequenced before X, Y is sequenced before B, and X precedes Y in
S, then B observes either the effects of A or a later modification
of M in its modification order.
void atomic_thread_fence(memory_order order);
order == memory_order_relaxed;
order == memory_order_acquire ||
order == memory_order_consume;
order == memory_order_release;
order == memory_order_acq_rel;
order == memory_order_seq_cst
.
void atomic_signal_fence(memory_order order);
atomic_thread_fence(order)
,
except that synchronizes with relationships are established only
between a thread and a signal handler executed in the same thread.
atomic_signal_fence
can be used to specify
the order in which actions performed by the thread become visible
to the signal handler.
atomic_thread_fence
, but
the hardware fence instructions that atomic_thread_fence
would have inserted are not emitted.